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Abstract
Disclosed is a flat panel display capable of enhancing a white balance by making a doping concentration or shape and size of drain offset regions of driving transistors different, in R, G and B unit pixels of each pixel. A flat panel display, comprises a plurality of pixels, where each of pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively. Each of the unit pixels includes a transistor with source/drain regions. Transistors of at least two unit pixels of the R, G and B unit pixels have drain regions of different geometric structures. In each unit pixel, a resistance value of the drain region of the transistor to drive a light-emitting device having the highest luminous efficiency among the transistors is higher than that of the drain region of a transistor to drive the light-emitting device having a relatively low luminous efficiency.
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Inventors: Koo, Jae-Bon; (Yongin-city, KR) ; Park, Sang-II; (Seoul, KR) ; Lee, UI-Ho; (Yongin-city, KR) ; Kim, Jin-Soo; (Yongin-city, KR) ; Jung, Jin-Woung; (Suwon-city, KR) ; Lee, Chang-Gyu; (Seoul, KR)
Correspondence Name and Address: MCGUIREWOODS, LLP
1750 TYSONS BLVD
SUITE 1800
MCLEAN
VA
22102
US
Assignee Name and Adress: Samsung SDI Co., Ltd.
Serial No.: 815792
Series Code: 10
Filed: April 2, 2004
U.S. Current Class: 345/82; 257/E21.703; 257/E27.111; 257/E29.279
U.S. Class at Publication: 345/082
Intern'l Class: G09G 003/32
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Foreign Application Data
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Date Code Application Number
Apr 17, 2003 KR 2003-0024425
Apr 17, 2003 KR 2003-0024447
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Claims
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What is claimed is:
1. A flat panel display, comprising: a plurality of pixels, each of the plurality of pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively, each of unit pixels including a transistor with source/drain regions, wherein transistors of at least two unit pixels of the R, G and B unit pixels have drain regions of different geometric structures.
2. The flat panel display according to claim 1, wherein each of the unit pixels further includes a light emitting device driven by the transistor, and a resistance value of a drain region of the transistor to drive the light emitting device having the highest luminous efficiency of the light emitting devices among the transistors in the unit pixels is higher than those of drain regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
3. The flat panel display according to claim 1, wherein the drain regions of the transistors of the R, G and B unit pixels are of a construction having a same length and a different width from one another, or a construction having a same width and a different length from one another.
4. The flat panel display according to claim 1, wherein the drain regions of the transistors of the R, G and B unit pixels are of zigzag shapes.
5. The flat panel display according to claim 1, wherein each unit pixel further includes a light emitting device driven by the transistor, and a drain region of a transistor to drive the light emitting device having the highest luminous efficiency of the light emitting devices among the transistors in the unit pixels has a longer length or a narrower width compared with lengths and widths of drain regions of transistors to drive light emitting devices having a relatively lower luminous efficiency.
6. The flat panel display according to claim 1, wherein the drain regions of the transistors of the R, G and B unit pixels include offset regions having different geometric structures from one another, respectively.
7. The flat panel display according to claim 6, wherein each unit pixel further includes a light-emitting device driven by the transistor, and a drain offset region of the transistor to drive the light emitting device having the highest luminous efficiency among the transistors in the unit pixels has a longer length or a narrower width in comparison with lengths and widths of drain offset regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
8. The flat panel display according to claim 1, wherein the drain offset regions of the transistors of the R, G and B unit pixels are of a construction having a same length and a different width from one another, or a construction having a same width and a different length from one another.
9. The flat panel display according to claim 8, wherein the drain offset regions of the transistors of the R, G and B unit pixels are of zigzag shapes.
10. The flat panel display according to claim 1, wherein the unit pixels further include light-emitting devices, respectively, and channel layers of the transistors controlling currents supplied to the light emitting devices of the unit pixels are of same size.
11. A flat panel display, comprising: a plurality of pixels, where each of the plurality of pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively, and where each of the unit pixels including a transistor with source/drain regions, wherein transistors of at least two unit pixels of the R, G and B unit pixels having drain regions of different resistance values.
12. The flat panel display according to claim 11, wherein the unit pixels further include light-emitting devices, respectively, and channel layers of the transistors controlling currents supplied to the light emitting devices of each unit pixel are of same size.
13. The flat panel display according to claim 12, wherein a resistance value of a drain region of the transistor to drive a light emitting device having the highest luminous efficiency among the transistors in the unit pixels is larger than those of drain regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
14. The flat panel display according to claim 11, wherein the drain regions of the R, G and B unit pixels include offset regions having different doping concentrations.
15. The flat panel display according to claim 14, wherein the unit pixels further include light emitting devices driven by the transistors, respectively, and a drain offset region of the transistor to drive a light emitting device having the highest luminous efficiency among the transistors in the unit pixels has a doping concentration lower than those of drain offset regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
16. The flat panel display according to claim 11, wherein the R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and the source/drain regions of the transistors include respective offset regions, where the source offset regions of the transistors of the R, G and B unit pixels comprise non-doped regions, and the drain offset regions of the transistors have different impurity doping concentrations in accordance with luminous efficiencies of the light emitting devices.
17. The flat panel display according to claim 11, wherein the R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and the source/drain regions of the transistors include respective offset regions, where the source offset regions of the transistors of the R, G and B unit pixels comprise regions doped with the same impurity concentration, and the drain offset regions of the transistors have different impurity doping concentrations in accordance with luminous efficiencies of the light emitting devices.
18. The flat panel display according to claim 11, wherein the R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, the source/drain regions of the transistors include respective offset regions, and the source/drain offset regions of the transistors of the R, G and B unit pixels have different impurity concentrations in accordance with luminous efficiencies of the light emitting devices.
19. The flat panel display according to claim 11, wherein at least two transistors of the transistors in the R, G and B unit pixels further include drain offset regions which are doped with impurities having different doping concentrations.
20. The flat panel display according to claim 19, wherein the R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and a drain offset region of a transistor to drive a light emitting device having the higher luminous efficiency in the at least two transistors has the doping concentration lower than that of a drain offset region of the other transistor.
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Description
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CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of Korean Patent Application No. 2003-24425 and 2003-24447, filed Apr. 17, 2003, the disclosure of which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
[0002] The present invention is related to a full-color flat panel display and, more particularly, to a flat panel display capable of embodying a white balance by changing a doping concentration or shape and size of an offset in a drain region and then varying a resistance value of the drain region in each unit pixel.
BACKGROUND OF THE INVENTION
[0003] Generally, as shown in FIG. 1, an organic light emitting diode (OLED) being a flat panel display includes a number of pixels 100 which are arranged in the form of a matrix, each pixel 100 comprising three unit pixels, that is, a unit pixel 110R for embodying a red color (R), a unit pixel 120G for embodying a green color (G) and a unit pixel 130B for embodying a blue color (B).
[0004] The R unit pixel 110R includes a red electroluminescence ("EL") device 115 including a red (R) light emitting layer, a driving transistor 113 for supplying a current to the red EL device 115, and a switching transistor 111 for switching the current supply from the driving transistor 113 to the red EL device 115.
[0005] The G unit pixel 120G includes a green EL device 125 including a green (G) light emitting layer, a driving transistor 123 for supplying a current to the green EL device 125, and a switching transistor 121 for switching the current supply from the driving transistor 123 to the green EL device 125.
[0006] The B unit pixel 130B includes a blue EL device 135 including a blue (B) light emitting layer, a driving transistor 133 for supplying a current to the blue EL device 135, and a switching transistor 131 for switching the current supply from the driving transistor 133 to the blue EL device 135.
[0007] Conventionally, the driving transistors 113, 123 and 133 of the R, G and B unit pixels 110R, 120G and 130B of an OLED have the same size, that is, the ratio W/L of the width W to the length L of the channel layer, and the order of the EL devices in the order of their luminous efficiencies is B, R and G unit pixel, where the B unit pixel has the lowest luminous efficiencies. Since the sizes of the driving transistors 113, 123 and 133 of the R, G, and B unit pixels 110R, 120G and 130B are same while luminous efficiencies of each R, G and B EL layer 115, 125 and 135 are different with one another, it was difficult to embody the white balance.
[0008] In order to embody the white balance, a relatively small quantity of current should be supplied to the EL device having high luminous efficiency, for example, green EL device, and a relatively large quantity of current should be supplied to the red and blue EL devices having low luminous efficiencies.
[0009] Here, since a current Id flowing to the EL device through the driving transistor begins to flow when the driving transistor is in the saturation state, the current is expressed as follows.
Id=Cox .mu.W{(Vg-Vth)}.sup.2/2L (1)
[0010] Therefore, one of the methods for controlling the current flowing to the EL device in order to embody the white balance is to make the sizes of the driving transistors of the R, G and B unit pixels, that is, the ratio W/L of the width W to the length L of the channel layer, different and then to control a quantity of the current flowing to the EL devices of the R, G and B unit pixels. A method for controlling the quantity of current flowing to the EL device in accordance with the size of the transistor is disclosed in the Japanese Laid-open Publication No. 2001-109399. In the Japanese patent, the sizes of the driving transistors of the R, G and B unit pixels are differently formed in accordance with the luminous efficiency of the EL device in each R, G and B unit pixel. That is, the quantity of the current flowing to the EL device of the R, G and B unit pixels is controlled by making the size of the driving transistor of the green unit pixel having a high luminous efficiency smaller than those of the driving transistors of the red or blue unit pixels having relatively low luminous efficiencies.
[0011] Another method to embody the white balance is to make the dimensions of the light emitting layers of R, G and B unit pixels different, which is disclosed in the Japanese Laid-open Patent Publication No. 2001-290441. In this Japanese patent, the same luminance is generated from the R, G and B unit pixels by making the light emitting areas different in accordance with light emitting efficiencies of the EL devices of the R, G and B unit pixels. That is, the same luminance is generated from the R, G and B unit pixels by making the light emitting areas of the R unit pixel or the B unit pixel having lower luminous efficiencies relatively larger than the light emitting areas of the G unit pixel having a relatively high luminous efficiency.
[0012] However, in the conventional method for embodying the white balance described above, since the light emitting area of the unit pixel having low luminous efficiency among the R, G and B unit pixels is enlarged, or the size of the transistor of the unit pixel having low luminous efficiency among the R, G and B unit pixels is increased, the area occupied in each pixel is increased, and therefore it is not easy to apply the method to a high definition flat panel display (FPD).
SUMMARY OF THE INVENTION
[0013] It is an aspect of the present invention to provide a flat panel display wherein a white balance can be embodied without increasing the area of a pixel.
[0014] A further aspect of the present invention provides a flat panel display wherein a white balance can be embodied by making resistance values of drain areas of driving transistors in each R, G and B unit pixel different.
[0015] It is yet another aspect of the present invention to provide a flat panel display wherein a white balance can be embodied by making doping concentrations of drain offset regions of driving transistors in each R, G and B unit pixel different.
[0016] Another aspect of the present invention provides a flat panel display wherein a white balance can be embodied by making geometric structures of drain regions of driving transistors in each R, G and B unit pixel different and changing resistance values of the drain regions.
[0017] An additional aspect of the present invention provides a flat panel display wherein a white balance can be embodied by making shapes and sizes of drain offset regions of driving transistors in each R, G and B unit pixel different.
[0018] According to an exemplary of embodiment of the present invention, there is provided a flat panel display, comprising a plurality of pixels, each of the pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively. Each of the unit pixels includes a transistor with source/drain regions, wherein the transistors of at least two unit pixels of the R, G and B unit pixels having drain regions of different geometric structures.
[0019] The unit pixels have different geometric structures which further include light-emitting devices, respectively, and channel layers of the transistors controlling currents supplied to the light emitting devices of the unit pixels are of the same size. A resistance value of a drain region of a transistor to drive a light emitting device having the highest luminous efficiency of the light emitting devices among the transistors in the unit pixels is higher than the resistance value of drain regions of transistors to drive light emitting devices having low luminous efficiency relatively.
[0020] The drain regions of the transistors of the R, G and B unit pixels are of a construction having the same length and different widths with one another, or a construction having the same width and different lengths with one another. The drain regions may have zigzag shapes.
[0021] The R, G and B unit pixels further include respective light emitting devices driven by the transistor. A drain region of a transistor to drive a light emitting device having the highest luminous efficiency of the light emitting devices among the transistors in the unit pixels has longer length or a narrower width compared with the lengths and widths of drain regions of transistors to drive light emitting devices having the relatively lower luminous efficiency.
[0022] The drain regions of the transistors of the R, G and B unit pixels include offset regions having different geometric structures from one another. The unit pixels further include respective light emitting devices driven by the transistors, and a drain offset region of a transistor to drive a light emitting device having the highest luminous efficiency among the transistors in the unit pixels has a longer length or a narrower width in comparison with the lengths and widths of drain offset regions of transistors to drive light emitting devices having relatively low luminous efficiency.
[0023] The drain offset regions of the transistors of the R, G and B unit pixels are of a construction having the same length and different widths from one another, or a construction having the same width and different lengths from one another. The drain offset regions may have zigzag shapes.
[0024] Another exemplary embodiment of the present invention provides a flat panel display, comprising a plurality of pixels, each of the pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively, and each of the unit pixels including a transistor with source/drain regions, wherein transistors of at least two unit pixels of the R, G and B unit pixels having drain regions of different resistance values.
[0025] The unit pixels having different resistance values further include light-emitting devices, respectively, and channel layers of the transistors controlling currents supplied to the light emitting devices of each unit pixel are of same size. A resistance value of a drain region of a transistor to drive a light emitting device having the highest luminous efficiency among the transistors in the unit pixels is larger than the resistance value of drain regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
[0026] The drain regions of the R, G and B unit pixels include offset regions having different doping concentrations. The unit pixels further include light emitting devices driven by the transistors, respectively, and a drain offset region of a transistor to drive a light emitting device having the highest luminous efficiency among the transistors in the unit pixels has a doping concentration lower than those of drain offset regions of transistors to drive light emitting devices having a relatively low luminous efficiency.
[0027] The R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and the source/drain regions of the transistors include respective offset regions. Source offset regions of the transistors of the R, G and B unit pixels comprise non-doped regions, and drain offset regions of the transistors have different impurity doping concentrations in accordance with luminous efficiencies of the light emitting devices.
[0028] The R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and the source/drain regions of the transistors include respective offset regions. Source offset regions of the transistors of the R, G and B unit pixels comprise regions doped with the same impurity concentration, and drain offset regions of the transistors have different impurity doping concentrations in accordance with the luminous efficiencies of the light emitting devices.
[0029] The R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, where the source/drain regions of the transistors include respective offset regions, and source/drain offset regions of the transistors of the R, G and B unit pixels have different impurity concentrations in accordance with luminous efficiencies of the light emitting devices.
[0030] The R, G and B unit pixels further include light emitting devices driven by the transistors, respectively, and at least two transistors of the transistors in the R, G and B unit pixels include offset regions which are doped with impurities having different doping concentrations. A drain offset region of a transistor to drive a light emitting device having the higher luminous efficiency in the at least two transistors has the doping concentration lower than that of a drain offset region of the other transistor. |
